1. Technical Field
The present invention relates to an address buffer and a method of buffering an address for a semiconductor memory apparatus. More particularly, the present invention relates to an address buffer and a method of buffering an address for a semiconductor memory apparatus, in which both a synchronous address buffering operation and an asynchronous address buffering operation can be performed.
2. Related Art
In general, a number of memory cells are included in a semiconductor memory apparatus and a data input and output operation is performed on the respective memory cells by using addresses. The address is input from the outside of the semiconductor memory apparatus. The semiconductor memory apparatus includes an address buffer, and an external address is converted into an internal address for use in the semiconductor memory apparatus. There are semiconductor memory apparatuses that use clocks, and that do not use clocks. Accordingly, a semiconductor memory apparatus that uses a clock includes a synchronous address buffer, and a semiconductor memory apparatus that does not use a clock includes an asynchronous address buffer.
Hereinafter, an address buffer according to the related art will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram illustrating the structure of an asynchronous address buffer in a semiconductor memory apparatus according to the related art.
The asynchronous address buffer includes an address input unit 2 that receives a buffering enable signal ben and an input address iad, and generates a latch input address lia; and an address latch unit 4 that receives an address strobing signal ast and the latch input address lia, and generates an asynchronous output address aoa.
At this time, the buffering enable signal ben is a low level enable signal, and the address strobing signal ast is a high level enable signal. The buffering enable signal ben can be generated by using a falling edge of a /CS (Chip Select) signal. In addition, the address strobing signal ast can be generated by using a falling edge of an /ADV signal (Valid Address Command) which is a command signal instructing an input operation of an address or a rising edge of a clock inputted in a state where the /ADV signal is enabled. However, the methods of generating the buffering enable signal ben and the address strobing signal ast are not limited thereto.
If the buffering enable signal ben is disabled, that is, the buffering enable signal ben has a high level voltage, the latch input address lia, which is the output of the address input unit 2 in response to the input of the input address iad, has a high level voltage regardless of the voltage level of the input address iad. At this time, the latch input address lia does not function as an address.
However, if the buffering enable signal ben is enabled, it has a low level voltage, the input address iad is driven in the address input unit 2 and is then outputted as the latch input address lia. At this time, the latch input address lia has the same phase as the input address iad.
Then, if the address strobing signal ast is enabled, the latch input address lia is input to the address latch unit 4. The address latch unit 4 drives the latch input address lia input at a rising edge time of the address strobing signal ast to generate the asynchronous output address aoa, and stores the generated asynchronous output address aoa. At this time, the asynchronous output address aoa has the same voltage level as the latch input address lia. However, the latch input address lia input in a state where the address strobing signal ast is disabled does not affect the asynchronous output address aoa, and at this time, the asynchronous output address aoa is an invalid address.
FIG. 2 is a block diagram illustrating a structure of the synchronous address buffer in a semiconductor memory apparatus according to the related art.
As shown in FIG. 2, the synchronous address buffer includes an address input unit 6 that receives the buffering enable signal ben and the input address iad and generates a first latch input address lia1; a clock synchronizing unit 8 that synchronizes the first latch input address lia1 with a clock clk and generates a second latch input address lia2; and an address latch unit 10 that receives a command pulse signal cmp and the second latch input address lia2 and generates the synchronous output address soa.
In this case, the command pulse signal cmp can be generated by using a rising edge of the clock input in a state where the /ADV signal is enabled. However, the method of generating the command pulse signal cmp is not limited thereto.
As in the asynchronous address buffer, if the buffering enable signal ben is disabled, the first latch input address lia1, which is the output of the address input unit 6 in response to the input of the input address iad, has a high level voltage regardless of the voltage level of the input address iad. At this time, the latch input address iad does not function as an address.
However, if the buffering enable signal ben is enabled, the input address iad is driven in the address input unit 6 and is then output as the first latch input address lia1. At this time, the first latch input address lia1 has the same phase as the input address iad.
Then, the clock synchronizing unit 8 receives the first latch input address lia1, drives the first latch input address lia1 at a rising edge time of the clock clk so as to generate the second latch input address lia2, and stores the generated second latch input address lia2. At this time, the second latch input address lia2 has the same phase as the first latch input address lia1. The voltage level of the second latch input address lia2 is maintained until the next rising edge time of the clock clk. The clock synchronizing unit 8 performs the above-described operation repeatedly for each rising edge time of the clock clk.
The address latch unit 10 receives the second latch input address lia2, drives the second latch input address lia2 at a rising edge time of the command pulse signal cmp so as to generate the synchronous output address soa, and stores the generated synchronous output address soa. At this time, the synchronous output address soa has the same phase as the second latch input address lia2. The voltage level of the synchronous output address soa is maintained until the next rising edge time of the command pulse signal cmp. The address latch unit 10 performs the above-described operation repeatedly for each rising edge time of the command pulse signal cmp.
FIG. 3 is a timing chart illustrating the operation of the asynchronous address buffer shown in FIG. 1. In order to describe the operation of the asynchronous address buffer according to whether a clock exists or not, an operation interval is divided into an interval where a clock is not input and an interval where a clock is input.
FIG. 3 shows the clock clk, the /CS signal, the /ADV signal, the input address iad, the address strobing signal ast, the buffering enable signal ben, the latch input address lia, and the asynchronous output address aoa. In this case, the /CS signal, the /ADV signal, and the buffering enable signal ben are low level enable signals. From FIG. 3, it can be understood that the buffering enable signal ben is enabled by a failing edge of the /CS signal. Further, it can be understood that the input address iad has a valid value and the address strobing signal ast is generated based on the /ADV signal. If the buffering enable signal ben is enabled, the latch input address lia has the same phase as the input address iad. In addition, the asynchronous output address aoa is generated from the latch input address lia at a rising edge time of the address strobing signal ast.
At this time, if the clock clk starts to be input, the interval of when the input address iad has a valid value is decreased, due to the following reason. Since a set-up time and a hold time of the input address iad for the clock clk are set in advance, an interval when the input address iad is valid cannot exceed a falling edge of the clock clk. During an interval of when the clock clk is not inputted, the input address iad maintains a valid value for a predetermined time even after the /ADV signal is disabled. However, if the clock clk starts to be inputted, the interval when the input address lad is valid is reduced. Therefore, an interval when the latch input address lia is valid is also reduced, and the address strobing signal ast latches an invalid value of the latch input address lia. Therefore, the asynchronous output address aoa has an invalid value.
FIG. 4 is a timing chart illustrating the operation of the synchronous address buffer shown in FIG. 2. As in FIG. 3, in order to describe the operation of the synchronous address buffer according to whether the clock exists or not, an operation interval is divided into an interval where the clock is not input, and an interval where the clock is input.
FIG. 4 shows the clock clk, the /CS signal, the /ADV signal, the input address iad, the first latch input address lia1, the second latch input address lia2, the command pulse signal cmp, and the synchronous output address soa. As in FIG. 3, the /CS signal and the /ADV signal are low level enable signals. From FIG. 3, it can be understood that the input address iad has a valid value based on the /ADV signal. In addition, it can be understood that the first latch input address lia1 is generated by the input address iad. The second latch input address lia2 is generated from the first latch input address lia1 at a rising edge time of the clock clk. If the first latch input address lia1 has a valid value at a rising edge time of the clock clk, the second latch input address lia2 also has a valid value with the same phase as the first latch input address lia1, and if the first latch input address lia1 has an invalid value, the second latch input address lia2 also has an invalid value. Similarly, the synchronous output address soa is also generated from the second latch input address lia2 at a rising edge time of the command pulse signal cmp.
At this time, it can be understood that the synchronous output address soa has an invalid value during an interval when the clock clk is not input. This is because the clock clk does not exist, and thus the second latch input address lia2 and the command pulse signal cmp are not generated.
As such, in the semiconductor memory apparatus according to the related art, if the clock is input, the synchronous address buffer operates normally, while the asynchronous address buffer cannot generate the normal output address. Further, if the clock is not inputted, the asynchronous address buffer operates normally, while the synchronous address buffer cannot generate the normal output address. According to the related art, there are technical limits in implementing a semiconductor memory apparatus, such as a Pseudo SRAM, where the clock is selectively input.